`include "defines.v"

module wb_reg(

    //  这一级主要是为指令提交设计，没有实际意义
    input wire               clk,
    input wire               rst,
    input wire               wb_stall_i,

    input  wire [`RAM_BUS]   wb_pc_i,
    input  wire [31:0]       wb_inst_i,
    input  wire              wb_rd_w_ena_i,
    input  wire [`REG_BUS]   wb_rd_w_addr_i,
    input  wire [`REG_WIDTH] wb_rd_w_data_i,
    input  wire              wb_halt_ena_i,
    input  wire              wb_skip_i,

    input  wire              wb_reg_valid_i,

    input  wire [`REG_WIDTH] wb_mstatus_i,
    input  wire [`REG_WIDTH] wb_mie_i,
    input  wire [`REG_WIDTH] wb_mtvec_i,
    input  wire [`REG_WIDTH] wb_mepc_i,
    input  wire [`REG_WIDTH] wb_mcause_i,
    input  wire [`REG_WIDTH] wb_mtval_i,
    input  wire [`REG_WIDTH] wb_mip_i,
    input  wire [`REG_WIDTH] wb_medeleg_i,
    input  wire [`REG_WIDTH] wb_mideleg_i,
    input  wire [`REG_WIDTH] wb_mscratch_i,

    output reg  [`RAM_BUS]   wb_pc_o,
    output reg  [31:0]       wb_inst_o,
    output reg               wb_rd_w_ena_o,
    output reg  [`REG_BUS]   wb_rd_w_addr_o,
    output reg  [`REG_WIDTH] wb_rd_w_data_o,
    output reg               wb_halt_ena_o,
    output reg               wb_skip_o,

    output reg               wb_reg_valid_o,

    output reg  [`REG_WIDTH] wb_mstatus_o,
    output reg  [`REG_WIDTH] wb_mie_o,
    output reg  [`REG_WIDTH] wb_mtvec_o,
    output reg  [`REG_WIDTH] wb_mepc_o,
    output reg  [`REG_WIDTH] wb_mcause_o,
    output reg  [`REG_WIDTH] wb_mtval_o,
    output reg  [`REG_WIDTH] wb_mip_o,
    output reg  [`REG_WIDTH] wb_medeleg_o,
    output reg  [`REG_WIDTH] wb_mideleg_o,
    output reg  [`REG_WIDTH] wb_mscratch_o


);


    always@(posedge clk)begin
        if(rst == `RST )begin
            wb_pc_o        <= 0;
            wb_inst_o      <= 0;
            wb_rd_w_ena_o  <= 0;
            wb_rd_w_addr_o <= 0;         
            wb_rd_w_data_o <= 0;
            wb_halt_ena_o  <= 0;
            wb_skip_o      <= 0;
            wb_reg_valid_o <= 0;
        end
        else if(wb_stall_i)begin
            wb_pc_o        <= wb_pc_o;
            wb_inst_o      <= wb_inst_o;
            wb_rd_w_ena_o  <= wb_rd_w_ena_o;
            wb_rd_w_addr_o <= wb_rd_w_addr_o;         
            wb_rd_w_data_o    <= wb_rd_w_data_o;
            wb_halt_ena_o  <= wb_halt_ena_o;
            wb_skip_o      <= wb_skip_o;
            wb_reg_valid_o <= wb_reg_valid_o;
        end
        else begin
            wb_pc_o        <= wb_pc_i;
            wb_inst_o      <= wb_inst_i;
            wb_rd_w_ena_o  <= wb_rd_w_ena_i;
            wb_rd_w_addr_o <= wb_rd_w_addr_i;         
            wb_rd_w_data_o    <= wb_rd_w_data_i;
            wb_halt_ena_o  <= wb_halt_ena_i;
            wb_skip_o      <= wb_skip_i;
            wb_reg_valid_o <= wb_reg_valid_i;
        end
    end

    always@(posedge clk)begin
        if(rst == `RST )begin
            wb_mstatus_o  <= 0;
            wb_mie_o      <= 0;
            wb_mtvec_o    <= 0;
            wb_mepc_o     <= 0;
            wb_mcause_o   <= 0;
            wb_mtval_o    <= 0;
            wb_mip_o      <= 0;
            wb_medeleg_o  <= 0;
            wb_mideleg_o  <= 0;
            wb_mscratch_o <= 0;
        end
        else if(wb_stall_i)begin
            wb_mstatus_o  <=  wb_mstatus_o ;
            wb_mie_o      <=  wb_mie_o     ;
            wb_mtvec_o    <=  wb_mtvec_o   ;
            wb_mepc_o     <=  wb_mepc_o    ;
            wb_mcause_o   <=  wb_mcause_o  ;
            wb_mtval_o    <=  wb_mtval_o   ;
            wb_mip_o      <=  wb_mip_o     ;
            wb_medeleg_o  <=  wb_medeleg_o ;
            wb_mideleg_o  <=  wb_mideleg_o ;
            wb_mscratch_o <=  wb_mscratch_o;
        end
        else begin
            wb_mstatus_o  <=  wb_mstatus_i ;
            wb_mie_o      <=  wb_mie_i     ;
            wb_mtvec_o    <=  wb_mtvec_i   ;
            wb_mepc_o     <=  wb_mepc_i    ;
            wb_mcause_o   <=  wb_mcause_i  ;
            wb_mtval_o    <=  wb_mtval_i   ;
            wb_mip_o      <=  wb_mip_i     ;
            wb_medeleg_o  <=  wb_medeleg_i ;
            wb_mideleg_o  <=  wb_mideleg_i ;
            wb_mscratch_o <=  wb_mscratch_i;
        end
    end




endmodule